AMD "RDNA 5" to Heavily Boost Shader Performance in Games with New Dual-Issue Pipeline
Source: Techpowerup.com
AMD is refining its RDNA 5 architecture, which is likely in its final stages of design. Thanks to a submission to the LLVM compiler, we are learning that AMD’s upcoming RDNA 5/UDNA architecture features architectural changes that will enhance compute utilization, resulting in significantly higher game shader performance. The codename for RDNA 5 is GFX1310, and it now implements a full Dual-Issue VALU pipeline for Wave32. This allows vector operations (VOPs) to be issued simultaneously to the GPU’s X and Y arithmetic logic unit (ALU) lanes. The new design expands the range of fused multiply-add (FMA) and other VOP instructions eligible for dual-issue and relaxes some register constraints, enabling compilers and shader code to perform more intensive floating-point work in Wave32 mode. This means the FP32 compute utilization of RDNA 5 can be much higher than before, greatly benefiting applications that are FP32-heavy, which means gamers are about to see a significant performance boost.
AMD originally implemented Dual Issue VALU in the RDNA 3 architecture with the Radeon RX 7000 series graphics cards. However, the pipeline was not fully functional, as the dual-issue implementation supported only a limited subset of VOP instructions, excluded several important FMA variants, required Wave32 mode and strict register-bank separation, and was often bypassed by compilers and not fully exposed to drivers. As a result, many shaders could not exploit X/Y pairing, and measured FP32 throughput often fell well below the hardware’s theoretical peak. This was detrimental to performance and reduced compute capability, especially in applications that rely heavily on FP32 compute. This is particularly true for modern games that process vertex and pixel shaders primarily using FP32 compute. With the new RDNA 5 design, gaming performance should align more closely with theoretical compute performance.
